CST 334 - Week 4

Memory Virtualization (Part 2)

This week we covered part 2 of memory virtualization. The primary takeaway dealt with a process called paging. Unlike segmentation, where chunks of memory can be various sizes, paging splits the memory up into equal-sized chunks called pages. Pages typically are small, usually 4kB (2^12 bytes) in size. Having memory sliced up into same-sized chunks eliminates external fragmentation, but internal fragmentation can still exist. The techniques of segmentation and paging can be combined.

The memory management unit contains a cache called the TLB, or translation lookaside buffer. This unit is essentially a map which translates virtual pages to physical pages. Since it is a physical cache near the CPU, it is not very large. It only contains mappings for the most recently accessed pages. If the CPU cannot find a page mapping in the TLB, a TLB miss occurs. When that happens, the TLB accesses the page table (via a pointer stored in a register), which is essentially a master map of all virtual to physical pages. The TLB loads itself with the mapping info and retries the original instruction, resulting in a TLB hit (and successful mapping). 

Of course, it is possible that a requested physical page is not located in memory, but rather in the disk's swap space, and a page fault (or miss) will occur. In that case, the TLB will raise an exception so that the operating system can address the page fault. There is often a background page daemon that automatically writes old pages to the disk (according to the system's page replacement policy) so that there are always physical pages available during page swapping.